Bonding pad is a component used to connect the internal elements of the chip to the external. Normally, the bonding pad is fabricated on the outermost layer of the chip. The bonding pad is made of conductive metal such as aluminum and copper, and it occupies 5% to 20% area of the chip die. With the continuous development of the integrated circuit, in the process under 0.5 μm, in order to effectively use the area of bonding pad and decrease the on-state of the power MOS transistor on-resistance (RDSon), the elements are needed to be placed under the bonding pad, i.e., CUP (Circuit Under Pad).
However, a problem encountered by the CUP process is that, during the packaging process, the bonding pad is subjected to great stress during the bonding process to the wires. In order to prevent the stress of wire bonding from affecting the performance of the chip, a plurality of metal layers or a single metal layer with 4 μm thickness is employed to release the stress.
As respecting to the CUP process using a plurality of metal layers, the disadvantage is that, each additional layer of metal will lead to an additional fabrication of through-hole and two layers of metal pattern, thus resulting an increase of cost by 20 to 40 dollars each IC wafer, which greatly reduce the competitiveness of IC.
In the 4 μm thick layer metal layer CUP production process, since modern semiconductor process requires the metal width to be continually decreased, the problem encountered by the production of thick metal layer is that, first, when the metal linewidth is less than 2 μm, Al2O3 residue is easily generated during the fabrication of Al—Cu metal structure with a thickness of 4 μm. In order to reduce the residue, deep etching is needed during the metal etching process, which requires that the photoresist for etching has a certain thickness. However, if the photoresist is too thick, after the exposure, it is impossible to obtain narrow etching width due to the resolution and other reasons, which forms a contradictory with narrow linewidth metal etching. Second, when the metallization process is completed, it is required to form a passivation layer on the surface of the metal layer. As for the metal strips dense area with narrow linewidth and deep depth, a key hole is easily formed at the gap between two metal strips during the production of the passivation layer. The key hole allows for retaining of the photoresist during the removing of the photoresist when etching the passivation layer, and the photoresist will expand during the subsequent alloy process, thus forming surface defects, such as photoresist residues 11 labeled in FIG. 1. In order to prevent the formation of the key hole, plasma enhanced chemical vapor deposition (PECVD) and high density plasma deposition (HDP) methods are often used to fully fill the metal condense area with the passivation layer. However, in this way, the increasing metal thickness will lead to an increasing passivation thickness and an increasing etching thickness, meanwhile, the deposition rate of HDP process is low, which leads to a longer deposition time and etching time and a higher cost.
The above reasons will increase the difficulty level of the thick metal structure during the conventional semiconductor process, it is thus necessary to make improvements to the conventional semiconductor process to overcome the above problems.